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• 8
• 1

Xiao/RISC-CPU-8-bits-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

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• 1
• 1

Xiao/awesome-dv

Awesome ASIC design verification

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• 0
• 1

Xiao/darkriscv

opensouce RISC-V implemented from scratch in one night!

• 1
• 0
• 0

Xiao/RV32IC-RTL-modeling-and-Verification

• 1
• 1
• 870

Xiao/tinyriscv forked from liangkangnan/tinyriscv

一个从零开始写的极简、非常易懂的RISC-V处理器核。

• 1
• 0
• 0

Xiao/FPGA

FPGA