我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
Open lab for Synopsys ICC2 block level implementation : from floorplan to chipfinish
来自github的大佬公开的项目ISP-pipeline-hdrplus
生成CRC并行计算verilog代码
GPT对话,Python基础编程示例:Excel读写追加处理,XML解析、JSON解析、FLV与MP4转换,PyQT界面应用程序开发示例等,https证书到期检测,糗百爬虫,pdf和图片互相转换,socket使用,百度OCR调用例子,IP及端口快速扫描。
Showing algorithm of ISP pipeline by summarizing the paper and code repetition.
https://blog.csdn.net/moon9999/article/details/125038466
ISP(Image Signal Processor)处理流程中的理论知识、相关算法、前沿及代表性文章、代码的介绍与分析。(陆续更新中......)
ImageSignalProcessing-ISP