# pcie7

**Repository Path**: speedz/pcie7

## Basic Information

- **Project Name**: pcie7
- **Description**: PCIe Controller HW/SW for ASIC Chip [2023]
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2023-01-31
- **Last Updated**: 2026-01-07

## Categories & Tags

**Categories**: Uncategorized

**Tags**: dev

## README

# PCIe Module Work Summary in 2023

## 🦀 2023.02 + 2023.03

- Get familiar with function requirements of the PCIe block.
- Read Controller IP PDFs and C10 PHY IP PDFs.
- Setup dev. environment (CTL 6.00a/VIP/C10 PHY 1.09b) 
- Release 202 PCIe CoreCfg_v1_0 with new settings from scratch based on CTL IP 6.00a.
  
  CoreCfg_v1_0 makes the following enhancements/debugs:
  
  [**EnhID1**] AER

  [**EnhID4**] RAS

  [**EnhID6**] Native HDMA

  [**BugID2**] Optimize Receive Completion Queue Mode (VC0)

  [**BugID4**] Full NCBE support

  [**EnhID7**] Proven Bandwidth match between PCIe and AXI based on simulation.
  
  File: **[bandwidth test](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_0/bandwidth)**
  
  File: **[cfg_v1_0 tcl script](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_0)** (zip with password)

## 🦑 2023.04

- [**BugID2**] Write testbench to simulate PCIe core behavior: inbound P + outbound NP bandwidth test. 
  
  It's proven that CPLs of OB NP-requests will NOT be blocked by IB P-requests within the PCIe core. 
  
  File: **[html version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID2/readme.md)**   or  **[pdf version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID2/CPL_TLPs_delivery_readme.pdf)**

- [**BugID4**] Collect trace information about 3D/2D GPU's AXI NCBE write transactions.
- [**BugID4**] Write testbench to verify PCIe core behavior: PCIe request conversion rule of outbound AXI NCBE writes and analysis of the performance impact.

  File: **[NCBE html version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID4/readme.md)**  or **[NCBE pdf version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID4/NCBE_readme.pdf)**

- [**EnhID4**] Simulate RAS D.E.S.
  
  File: **[RAS readme](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID4/readme.md)** 

- [**EnhID1**] Simulate AER, and write AER driver support guide.
  
  File: **[AER driver support guide](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID1/readme.md)**

- [**EnhID2**] Simulate Multiple MSI.
  
  File: **[Multiple MSI Considerations](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID2/Multiple_MSI_Considerations.md)**
  
- Release 202 PCIe CoreCfg_v1_1 with minor changes.
  
  File: **[cfg_v1_1 tcl script](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_1)** (zip with password)

## 🛳 2023.05

- Release 202 PCIe CoreCfg_v1_2 with minor changes.
  
  File: **[cfg_v1_2 tcl script](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_2)** (zip with password)

- [**HowID1**] How to set the number of lanes in the PCIe link (requested by Hu-YM).

  File: **[how to set lane number](https://gitee.com/speedz/pcie7/tree/master/HowtoList/HowID1/readme.md)**

- [**EnhID10**] Function Level Reset (FLR).

  File: **[FLR considerations](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID10/readme.md)**


- [**201CodeExplore**] 201 interrupt known issues and fixes.
  
  File: **[201_interrupt_known_issues_fixes](https://gitee.com/speedz/pcie7/blob/master/201Explore/201_interrupt_known_issues.md)**  

## 🏄 2023.06

- [**201CodeExplore**] 201 on-chip-bus latency.
  
  File: **[201_high_latency_on-chip-bus_data-path_for_register_access](https://gitee.com/speedz/pcie7/blob/master/201Explore/201_high_latency_on-chip-bus_data-path_for_register_access.md)**

- [**201CodeExplore**] 201 device initialization time limit.
  
  File: **[201_initialization_time_limit](https://gitee.com/speedz/pcie7/blob/master/201Explore/201_initialization_time_limit.md)**

- [**EnhID2**] 202 New Feature: Add Multiple MSI Support.
  
  File: **[202_Multiple_MSI_Support_Guide](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID2/202_Multiple_MSI_Support.md)**

  File: **[202_MSI_QA](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID2/MSI_QA.md)**